DDR2 SDRAM
Key Properties
- 4-bit pre-fetch
- SSTL-18
- 667MHz per Pin
The advantage of DDR2 over DDR SDRAM is the ability for much higher clock speeds, due to design improvements. With a clock frequency of 100 MHz, "SDR-SDRAM" transfers data on every rising edge of the clock pulse, thus achieving an effective 100 MHz data transfer rate. Unlike SDR, both DDR and DDR2 are double pumped; they transfer data on the rising and falling edges of the clock, at points of 0.0 V and 2.5 V (1.8 V for DDR2), achieving an effective rate of 200 MHz (and a theoretical bandwidth of 1.6 GB/s) with the same clock frequency. DDR2's clock frequency is further boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 prefetch buffer is 4 bits wide, whereas it's 2 bits wide for DDR and 8 bits wide for DDR3.
As the diagram above demonstrates, DDR2 SDRAM achieves high-speed operation by 4-bit prefetch architecture.
In 4-bit prefetch architecture,
DDR2 SDRAM can read / write 4 times the amount of data as an external bus from / to the memory cell array for every clock, and can be operated 4 times faster than the internal bus operation frequency.
Power savings are achieved primarily due to an improved manufacturing process, resulting in a drop in operating voltage (1.8 V compared to DDR's 2.5 V). The lower memory clock frequency could also help — DDR2 can use a real clock frequency 1/2 that of SDRAM whilst maintaining the same bandwidth.
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